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19-2437; Rev 1; 10/02
KIT ATION EVALU LE B AVAILA
4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver
General Description Features
o High-Speed 26MHz with SPI-/QSPI-TM/ MICROWIRETM-Compatible Serial Interface o 2.7V to 5.5V Operation o Drives Four Monocolor or Two Bicolor CathodeRow 5 7 Matrix Displays o Built-In ASCII 104-Character Font o 24 User-Definable Characters Available o Automatic Blinking Control for Each Segment o 36A Low-Power Shutdown (Data Retained) o 16-Step Digital Brightness Control o Display Blanked on Power-Up o Slew-Rate-Limited Segment Drivers for Lower EMI o 36-Pin SSOP and 40-Pin DIP Packages
MAX6952
The MAX6952 is a compact cathode-row display driver that interfaces microprocessors to 5 7 dot-matrix LED displays through an SPITM-compatible serial interface. The MAX6952 drives up to four digits (140 LEDs). Included on chip are an ASCII 104-character font, multiplex scan circuitry, column and row drivers, and static RAM that stores each digit, as well as font data for 24 user-definable characters. The segment current for the LEDs is set by an internal digit-by-digit digital brightness control. The device includes a low-power shutdown mode, segment blinking (synchronized across multiple drivers, if desired), and a test mode that forces all LEDs on. The LED drivers are slew rate limited to reduce EMI. For a 2-wire interfaced version, refer to the MAX6953 data sheet. An EV kit is available for the MAX6952.
Applications
Message Boards Medical Equipment Industrial Displays Audio/Video Equipment Gaming Machines
PART MAX6952EAX MAX6952EPL
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 36 SSOP 40 PDIP
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configurations appear at end of data sheet.
Typical Application Circuit
DIGIT 0 DIGIT 1 O19 O20 O21 O22 O23 O0 O1 O2 O3 O4 O5 O6 C1 C2 C3 C4 C5
3.3V
V+ V+ 100nF
47F
GND GND GND
3.3V
MAX6952
4.7k CLK DIN CS DOUT BLINK OSC ISET CSET 26pF RSET 53.6k
O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23
O14 O15 O16 O17 O18 O0 O1 O2 O3 O4 O5 O6
C1 C2 C3 C4 C5
R1 R2 R3 R4 R5 R6 R7
R1 R2 R3 R4 R5 R6 R7
DIGIT 2 O14 O15 O16 O17 O18 O7 O8 O9 O10 O11 O12 O13 C1 C2 C3 C4 C5 O19 O20 O21 O22 O23 O7 O8 O9 O10 O11 O12 O13
DIGIT 3 C1 C2 C3 C4 C5
R1 R2 R3 R4 R5 R6 R7
R1 R2 R3 R4 R5 R6 R7
________________________________________________________________ Maxim Integrated Products
1
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952
ABSOLUTE MAXIMUM RATINGS
Voltage (with respect to GND) V+ .............................................................................-0.3V to +6V All Other Pins................................................-0.3V to (V+ + 0.3V) O0-O13 Sink Current ....................................................... 500mA O14-O23 Source Current .................................................. 50mA Continuous Power Dissipation (TA = +70C) 36-Pin SSOP (derate 11.8mW/C above +70C) .....941.2mW 40-Pin PDIP (derate 16.7mW/C above +70C)........1333mW Operating Temperature Range (TMIN, TMAX) ......-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Typical operating circuit, V+ = 3.0V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER Operating Supply Voltage Shutdown Supply Current SYMBOL V+ ISHDN Shutdown mode, all digital inputs at V+ or GND TA = TMIN to TMAX TA = +25C 36 CONDITIONS MIN 2.7 TYP MAX 5.5 100 80 UNITS V A
Operating Supply Current Master Clock Frequency (OSC Internal Oscillator) Master Clock Frequency (OSC External Oscillator) Dead Clock Protection Frequency OSC Internal/External Detection Threshold OSC High Time OSC Low Time Slow Segment Blink Period (OSC Internal Oscillator) Fast Segment Blink Period (OSC Internal Oscillator) Fast or Slow Segment Duty Cycle Column Drive Source Current Segment Current Slew Rate Segment Drive Current Matching (Within IC)
I+
All segments on, intensity set to full, internal oscillator, DOUT open circuit, no display load connected, blink open circuit OSC = RC oscillator, RSET = 53.6k, CSET = 26pF OSC overdriven externally 1
12
16
mA
fOSC fOSC fOSC VOSC tCH tCL fSLOWBLINK fFASTBLINK
4 8 90 1.7 50 50
MHz MHz kHz V ns ns
OSC = RC oscillator, RSET = 53.6k, CSET = 26pF OSC = RC oscillator, RSET = 53.6k, CSET = 26pF (Note 2) 49.5 -32
1 0.5 50.5 -48 12.5 4
s s % mA mA/s %
ICOLUMN ISEG/t ISEG
VLED = 2.4V, V+ = 3.0V, TA = +25C TA = +25oC TA = +25oC
2
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver
DC ELECTRICAL CHARACTERISTICS (continued)
(Typical operating circuit, V+ = 3.0V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER LOGIC INPUTS AND OUTPUTS Input High Voltage DIN, CLK, CS Input Low Voltage DIN, CLK, CS Input Leakage DIN, CLK, CS, OSC DOUT Output Low Voltage DOUT Output High Voltage Blink Output Low Voltage CLK Clock Period CLK Pulse Width High CLK Pulse Width Low CS Fall to CLK Rise Setup Time CLK Rise to CS Rise Hold Time DIN Setup Time DIN Hold Time CS Pulse High DOUT Propagation Delay VIH VIL IIH, IIL VOLDO VOHDO VOLBK tCP tCH tCL tCSS tCSH tDS tDH tCSW tDO CLOAD = 10pF ISINK = 1.6mA ISOURCE = 1.6mA ISINK = 1.6mA 38.4 19 19 9.5 5 9.5 0 19 19 V+ - 0.4V 0.4 -2 +0.1 2.4 0.4 +2 0.4 V V A V V V ns ns ns ns ns ns ns ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX6952
TIMING CHARACTERISTICS (Figure 1)
Note 1: All parameters tested at TA = +25C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design.
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952
Typical Operating Characteristics
(Typical application circuit, V+ = 3.3V, LED forward voltage = 2.4V, scan limit set to 4 digits, TA = +25C, unless otherwise noted.)
INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE
MAX6952 toc01
INTERNAL OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE
MAX6952 toc02
INTERNAL OSCILLATOR WAVEFORM AT OSC
MAX6952 toc03
4.30 OSCILLATOR FREQUENCY (MHz)
4.4 OSCILLATOR FREQUENCY (MHz) 4.3 4.2 4.1 4.0 3.9 3.8
2.5
4.20
V+ = 2.7V
2.0 VOLTAGE AT OSC (V)
4.10 V+ = 3.3V 4.00 V+ = 5V 3.90
1.5
1.0
0.5 3.7
3.80 -40 -20 0 20 40 60 80 TEMPERATURE (C)
3.6 2.5 3.5 4.5 5.5 SUPPLY VOLTAGE (V)
0 0 200 400 TIMELINE (ns) 600 800
DEAD CLOCK OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE
MAX6952 toc04
SEGMENT SOURCE CURRENT vs. SUPPLY VOLTAGE
MAX6952 toc05
105 OSCILLATOR FREQUENCY (kHz)
1.01 CURRENT NORMALIZED TO 40mA 1.00 0.99 0.98 0.97 0.96 0.95
100
95
90
85
80 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
WAVEFORMS AT O2 (PIN 3) AND O14 (PIN 28) 15/16 INTENSITY
MAX6952 toc06
GROUND FOR ANODE (PIN O14)
GROUND FOR CATHODE (PIN O3)
220ms/div
4
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver
Pin Description
PIN SSOP 1, 2, 3, 6-14, 23, 24 4, 5, 16 15 17 18 PDIP 1, 2, 3, 7-15, 26, 27 4, 5, 6, 18 17 19 20 NAME O0 to O13 GND ISET BLINK DIN FUNCTION LED Cathode Drivers. O0 to O13 outputs sink current from the display's cathode rows. Ground Segment Current Setting. Connect ISET to GND through series resistor RSET to set the peak current. Blink Clock Output. Output is open drain. Serial Data Input. Data is loaded into the internal 16-bit shift register on the rising edge of the CLK. Serial-Clock Input. On the rising edge of CLK, data is shifted into the internal shift register. On the falling edge of CLK, data is clocked out of DOUT. CLK input is active only while CS is low. Serial Data Output. Data clocked into DIN is output to DOUT 15.5 clock cycles later. Data is clocked out on the rising edge of CLK. Output is push-pull. Chip-Select Input. Serial data is loaded into the shift register while CS is low. The last 16 bits of serial data are latched on CS's rising edge. Multiplex Clock Input. To use the internal oscillator, connect capacitor CSET from OSC to GND. To use the external clock, drive OSC with a 1MHz to 8MHz CMOS clock. LED Anode Drivers. O14 to O23 outputs source current to the display's anode columns. Positive Supply Voltage. Bypass V+ to GND with a 47F bulk capacitor and a 0.1F ceramic capacitor.
MAX6952
19
21
CLK
20
22
DOUT
21
23
CS
22
24
OSC
25-31, 34, 35, 36 32, 33
28-34, 38, 39, 40 35, 36, 37
O14 to O23 V+
Detailed Description
The MAX6952 is a serially interfaced display driver that can drive four digits of 5 7 cathode-row dot-matrix displays. The MAX6952 can drive either four monocolor digits (Table 1) or two bicolor digits (Table 2). The MAX6952 includes a 128-character font map comprising 104 predefined characters and 24 user-definable characters. The predefined characters follow the Arial font, with the addition of the following common symbols: , , , , , , , and . The 24 user-definable characters are uploaded by the user into on-chip RAM through the serial interface and are lost when the device is powered down. Figure 1 is the MAX6952 functional diagram.
Serial Interface
The MAX6952 communicates through an SPI-compatible 4-wire serial interface. The interface has three inputs, clock (CLK), chip select (CS), and data in (DIN), and one output, data out (DOUT). CS must be low to clock data into or out of the device, and DIN must be stable when sampled on the rising edge of CLK. DOUT is stable on the rising edge of CLK. Note that while the SPI protocol expects DOUT to be high impedance when the MAX6952 is not being accessed, DOUT on the MAX6952 is never high impedance.
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952
Table 1. Connection Scheme for Four Monocolor Digits
DIGIT O0 O1 O2 O3 1 2 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 -- Digit 2 rows (cathodes) R1 to R7 Digit 3 rows (cathodes) R1 to R7 Digit 0 columns (anodes) C1 to C5 Digit 2 columns (anodes) C1 to C5 Digit 1 columns (anodes) C6 to C10 Digit 3 columns (anodes) C6 to C10 Digit 0 rows (cathodes) R1 to R7 Digit 1 rows (cathodes) R1 to R7 --
Table 2. Connection Scheme for Two Bicolor Digits
DIGIT O0 O1 O2 O3 O4 1 2 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 -- Digit 1 rows (cathodes) R1 to R14 Digit 0 columns (anodes) C1 to C10 - the 5 green anodes - the 5 red anodes Digit 1 columns (anodes) C1 to C10 - the 5 green anodes - the 5 red anodes Digit 0 rows (cathodes) R1 to R14 --
Table 3. Serial-Data Format (16 Bits)
D15 R/W D14 D13 D12 D11 D10 D9 D8 D7 MSB D6 D5 D4 D3 DATA D2 D1 D0 LSB ADDRESS
ISET
CURRENT SOURCE DIVIDER/ COUNTER NETWORK
PWM BRIGHTNESS CONTROL ROW MULTIPLEXER
CLK and DIN may be used to transmit data to other peripherals. The MAX6952 ignores all activity on CLK and DIN except when CS is low.
LED DRIVERS O0 TO O23
OSC
Control and Operation Using the 4-Wire Interface Controlling the MAX6952 requires sending a 16-bit word. The first byte, D15 through D8, is the command byte (Table 3), and the second byte, D7 through D0, is the data byte. Connecting Multiple MAX6952s to the 4-Wire Bus Multiple MAX6952s may be daisy-chained by connecting the DOUT of one device to the DIN of the next, and driving CLK and CS lines in parallel (Figure 6). Data at DIN propagates through the internal shift registers and appears at DOUT 15.5 clock cycles later, clocked out on the falling edge of CLK. When sending commands to daisy-chained MAX6952s, all devices are accessed at the same time. An access requires (16 x n) clock cycles, where n is the number of MAX6952s connected together. To update just one device in a daisy-chain, the user can send the no-op command (0x00) to the others. Writing Device Registers The MAX6952 contains a 16-bit shift register into which DIN data are clocked on the rising edge of SCLK, when CS is low. When CS is high, transitions on SCLK have no effect. When CS goes high, the 16 bits in the shift
CHARACTER GENERATOR RAM
CHARACTER GENERATOR ROM
BLINK
BLINK SPEED SELECT CONFIGURATION REGISTERS RAM
MAX6952
CLK CS DIN DOUT SERIAL INTERFACE
Figure 1. Functional Diagram
6
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver
register are parallel loaded into a 16-bit latch. The 16 bits in the latch are then decoded and executed. The MAX6952 is written to using the following sequence: 1) Take CLK low. 2) Take CS low. This enables the internal 16-bit shift register. 3) Clock 16 bits of data into DIN, D15 first to D0 last, observing the setup and hold times. Bit D15 is low, indicating a write command. 4) Take CS high (while CLK is still high after clocking in the last data bit). 5) Take CLK low. Figure 3 shows a write operation when 16 bits are transmitted. If fewer or greater than 16 bits are clocked into the MAX6952 between taking CS low and taking CS high again, the MAX6952 stores the last 16 bits received, including the previous transmission(s). The general case is when n bits (where n > 16) are transmitted to the MAX6952. The last bits comprising bits {n-15} to {n} are retained and are parallel loaded into the 16-bit latch as bits D15 to D0, respectively (Figure 4). Reading Device Registers Any register data within the MAX6952 may be read by sending a logic high to bit D15. The sequence is: 1) Take CLK low. 2) 3) Take CS low. This enables the internal 16-bit shift register. Clock 16 bits of data into DIN, D15 first to D0 last, observing the setup and hold times. Bit D15 is high, indicating a read command and bits D14 through D8 contain the address of the register to read. Bits D7 to D0 contain dummy data, which is discarded. Take CS high. Positions D7 through D0 in the shift register are now loaded with the data in the register addressed by bits D15 through D8. Bits Take CLK low. Issue another read or write command (which can be a no-op), and examine the bit stream at DOUT; the second 8 bits are the contents of the register addressed by bits D14 through D8 in step 3. is represented by 2 bytes of memory, 1 byte in plane P0 and the other in plane P1. The digit registers are mapped so that a digit's data can be updated in plane P0, or plane P1, or both planes at the same time (Table 4). If the blink function is disabled through the Blink Enable Bit E (Table 9) in the configuration register, then the digit register data in plane P0 is used to multiplex the display. The digit register data in P1 is not used. If the blink function is enabled, then the digit register data in both plane P0 and plane P1 are alternately used to multiplex the display. Blinking is achieved by multiplexing the LED display using data planes P0 and P1 on alternate phases of the blink clock (Table 10). The data in the digit registers does not control the digit segments directly. Instead, the register data is used to address a character generator, which stores the data of a 128-character font (Table 14). The lower 7 bits of the digit data (D6 to D0) select the character from the font. The most-significant bit of the register data (D7) selects whether the font data is used directly (D7 = 0) or whether the font data is inverted (D7 = 1). The inversion feature can be used to enhance the appearance of bicolor displays by displaying, for example, a red character on a green background.
MAX6952
Display Blink Mode
The display blinking facility, when enabled, makes the driver flip automatically between displaying the digit register data in planes P0 and P1. If the digit register data for any digit is different in the two planes, then that digit appears to flip between two characters. To make a character appear to blink on or off, write the character to one plane, and use the blank character (0x20) for the other plane. Once blinking has been configured, it continues automatically without further intervention.
Blink Speed
The blink speed is determined by frequency of the multiplex clock, OSC, and by setting the Blink Rate Selection Bit B (Table 8) in the configuration register. The Blink Rate Selection Bit B sets either fast or slow blink speed for the whole display.
4)
5) 6)
Initial Power-Up
On initial power-up, all control registers are reset, the display is blanked, intensities are set to minimum, and shutdown is enabled (Table 5).
Digit Registers
The MAX6952 uses eight digit registers to store the characters that the user wishes to display on the four 5 7 LED digits. These digit registers are implemented with two planes of 4 bytes, called P0 and P1. Each LED digit
Configuration Register
The configuration register is used to enter and exit shutdown, select the blink rate, globally enable and disable the blink function, globally clear the digit data, and reset the blink timing (Table 6).
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952
CS tCSW
tCSS
tCL
tCH
tCP
tCSH
CLK tDS DIN
tDH D14 D1 tDO D0
D15
DOUT TIMING NOT TO SCALE.
D15
Figure 2. Timing Diagram
CS
CLK DIN D15 =0 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
D15 = 0
Figure 3. 16-Bit Write Transmission to the MAX6952
CS
CLK
N-15
DIN
N-14
N-13
N-12
N-11
N-10
N-9
N-8
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N
BIT 1
BIT 2
DOUT TIMING NOT TO SCALE.
N-31
N-30
N-29
N-28
N-27
N-26
N-25
N-24
N-23
N-22
N-21
N-20
N-19
N-18
N-17
N-16
N-15
Figure 4. Transmission of More than 16 Bits to the MAX6952
8
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952
Table 4. Register Address Map
REGISTER D15 No-Op Intensity10 Intensity32 Scan-Limit Configuration User-Defined Fonts Factory reserved. Do not write to this. Display Test Digit 0 Plane P0 Digit 1 Plane P0 Digit 2 Plane P0 Digit 3 Plane P0 Digit 0 Plane P1 Digit 1 Plane P1 Digit 2 Plane P1 Digit 3 Plane P1 Write Digit 0 Plane P0 and Plane P1 with Same Data (Reads as 0x00) Write Digit 1 Plane P0 and Plane P1 with Same Data (Reads as 0x00) Write Digit 2 Plane P0 and Plane P1 with Same Data (Reads as 0x00) Write Digit 3 Plane P0 and Plane P1 with Same Data (Reads as 0x00) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W D14 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ADDRESS (COMMAND BYTE) D13 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D10 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 D9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x20 0x21 0x22 0x23 0x40 0x41 0x42 0x43 0x60 0x61 0x62 0x63 HEX CODE
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952
Shutdown Mode (S Data Bit D0) Format The S bit in the configuration register selects shutdown or normal operation (Table 7). The display driver can be programmed while in shutdown mode, and shutdown mode is overridden when in display test mode. For normal operation, the S bit should be set to 1. Blink Rate Selection (B Data Bit D2) Format The B bit in the configuration register selects the blink rate. This is the speed that the segments alternate between plane P0 and plane P1 refresh data. The blink rate is determined by the frequency of the multiplex clock OSC, in addition to the setting of the B bit (Table 8). Global Blink Enable/Disable (E Data Bit D3) Format The E bit globally enables or disables the blink feature of the device (Table 9). When blink is globally enabled, then the digit data in both planes P0 and P1 are used to control the display (Table 10).
Table 5. Initial Power-Up Register Status
REGISTER Intensity10 Intensity32 Scan Limit Configuration POWER-UP CONDITION 1/16 (min on) 1/16 (min on) Display 4 digits: 0 1 2 3 Shutdown enabled, blink speed is slow, blink disabled Address 0x80; pointing to the first user-defined font location Normal operation Blank digit (0x20) Blank digit (0x20) Blank digit (0x20) Blank digit (0x20) Blank digit (0x20) Blank digit (0x20) Blank digit (0x20) Blank digit (0x20) ADDRESS CODE (HEX) 0x01 0x02 0x03 0x04 REGISTER DATA D7 0 0 X 0 D6 0 0 X X D5 0 0 X 0 D4 0 0 X 0 D3 0 0 X 0 D2 0 0 X 0 D1 0 0 X X D0 0 0 1 0
User-Defined Font Address Pointer Display Test Digit 0 Plane P0 Digit 1 Plane P0 Digit 2 Plane P0 Digit 3 Plane P0 Digit 0 Plane P1 Digit 1 Plane P1 Digit 2 Plane P1 Digit 3 Plane P1
0x05 0x07 0x20 0x21 0x22 0x23 0x40 0x41 0x42 0x43
1 X 0 0 0 0 0 0 0 0
0 X 0 0 0 0 0 0 0 0
0 X 1 1 1 1 1 1 1 1
0 X 0 0 0 0 0 0 0 0
0 X 0 0 0 0 0 0 0 0
0 X 0 0 0 0 0 0 0 0
0 X 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
Table 6. Configuration Register Format
REGISTER Configuration Register REGISTER DATA D7 P D6 X D5 R D4 T D3 E D2 B D1 X D0 S
Table 7. Shutdown Control (S Data Bit D0) Format
MODE Shutdown Mode Normal Operation REGISTER DATA D7 P P D6 X X D5 R R D4 T T D3 E E D2 B B D1 X X D0 0 1
10
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver
When blink is globally disabled, then only the digit data in plane P0 is used to control the display. The digit data in plane P1 is ignored. Global Blink Timing Synchronization (T Data Bit D4) Format By setting the T bit in multiple MAX6952s at the same time (or in quick succession), the blink timing can be synchronized across all the devices (Table 11). Note that the display multiplexing sequence is also reset, which might give rise to a one-time display flicker when the register is written. Global Clear Digit Data (R Data Bit D5) Format When global digit data clear is set, the digit data for both planes P0 and P1 for all digits is cleared (Table 12). Blink Phase Readback (P Data Bit D7) Format When the configuration register is read, the P bit reflects the state of the blink output pin at that time (Table 13).
MAX6952
Character Generator Font Mapping
The font is a 5 7 matrix comprising 104 characters in ROM, and 24 user-definable characters. The selection from the total of 128 characters is represented by the lower 7 bits of the 8-bit digit registers. The most-significant bit, shown as x in the ROM map below, is zero to light LEDs as shown by the black segments in Table 14, and 1 to display the inverse. The character map follows the Arial font for 96 characters in the x0101000 through x1111111 range. The first
DOUT CLK MICROCONTROLLER CS
DIN CLK CS MAX6952
DOUT
DIN CLK CS MAX6952
DOUT
DIN CLK CS MAX6952 DOUT
DIN
Figure 6. MAX6952 Daisy-Chain Connection
Table 8. Blink Rate Selection (B Data Bit D2) Format
MODE Slow blinking (Segments are refreshed using plane P0 for 1s, plane P1 for 1s, for OSC = 4MHz.)
REGISTER DATA D7 P D6 X D5 R D4 T D3 E D2 0 D1 X D0 S
Table 9. Global Blink Enable/Disable (E Data Bit D3) Format
MODE Blink function is disabled. Blink function is enabled. REGISTER DATA D7 P P D6 X X D5 R R D4 T T D3 0 1 D2 B B D1 X X D0 S S
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver
Table 10. Digit Register Mapping with Blink Globally Enabled
SEGMENT'S BIT SETTING IN PLANE P1 0 0 SEGMENT'S BIT SETTING IN PLANE P0 0 1 SEGMENT BEHAVIOR Segment off Segment on only during the 1st half of each blink period Segment on only during the 2nd half of each blink period Segment on
1 1
0 1
indirectly accesses the font data. The font address pointer can be written, setting one of 120 addresses between 0x00 and 0xF7, but cannot be read back. The font data is written to and read from the MAX6952 indirectly, using this font address pointer. Unused font locations can be used as general-purpose scratch RAM, bearing in mind that the font registers are only 7 bits wide, not 8. Table 15 shows how the single user-defined font register 0x05 is used to set the font address pointer, write font data, and read font data. A read action always returns font data from the font address pointer position. A write action sets the 7-bit font address pointer if the MSB is set, or writes 7-bit font data to the font address pointer position if the MSB is clear. The font address pointer autoincrements after a valid access to the user-definable font data. Autoincrementing allows the 120 font data entries to be written and read back very quickly because the font pointer address need only be set once. When the last data location 0xF7 is written, the font address pointer autoincrements to address 0x80. If the font address pointer is set to an out-of-range address by writing data in the 0xF8 to 0xFF range, then address 0x80 is set instead (Table 16). Table 17 shows the user-definable font pointer base addresses.
MAX6952
32 characters map the 24 user-definable positions (RAM00 to RAM23), plus eight extra common characters in ROM.
User-Defined Fonts
The 24 user-definable characters are represented by 120 entries of 7-bit data, five entries per character, and are stored in the MAX6952's internal RAM. The 120 user-definable font data entries are written and read through a single register, address 0x05. An autoincrementing font address pointer in the MAX6952
Table 11. Global Blink Timing Synchronization (T Data Bit D4) Format
MODE Blink timing counters are unaffected. Blink timing counters are reset on the rising edge of CS. REGISTER DATA D7 P P D6 X X D5 R R D4 0 1 D3 E E D2 B B D1 X X D0 S S
Table 12. Global Clear Digit Data (R Data Bit D5) Format
MODE Digit data for both planes P0 and P1 are unaffected. Digit data for both planes P0 and P1 are cleared on the rising edge of CS. REGISTER DATA D7 P P D6 X X D5 0 1 D4 T T D3 E E D2 B B D1 X X D0 S S
Table 13. Blink Phase Readback (P Data Bit D7) Format
MODE P1 Blink Phase P0 Blink Phase REGISTER DATA D7 0 1 D6 X X D5 R R D4 T T D3 E E D2 B B D1 X X D0 S S
12
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver
Table 14. Character Map
MSB x000 LSB x001 x010 x011 x100 x101 x110 x111
Table 18 shows an example of data (characters 0, 1, and 2) being stored in the first three user-defined font locations, illustrating the orientation of the data bits. Table 19 shows the six sequential write commands required to set a MAX6953's font character RAM02 with the data to display character 2 given in the font RAM illustration above.
MAX6952
0000
RAM00
RAM16
0001
RAM01
RAM17
Multiplex Clock and Blink Timing
The OSC pin can be fitted with capacitor CSET to GND (to use the internal RC multiplex oscillator), or driven by an external clock. The multiplex clock frequency determines the multiplex scan rate and the blink timing. The display scan rate is calculated by dividing the frequency at OSC by 5600. With OSC at 4 MHz, each display digit is enabled for 100s and the display scan rate is 714.29Hz. The on-chip oscillator may be accurate enough for applications using a single device. If an exact blink rate is required, use an external clock ranging between 1MHz and 8MHz to drive OSC. The OSC inputs of multiple MAX6952s can be tied together to a common external clock to make the devices blink at the same rate. The relative blink phasing of multiple MAX6952s can be synchronized by setting the T bit in the control register for all the devices in quick succession (Table 11). If the serial interfaces of multiple MAX6952s are daisychained by connecting DOUT of one device to DIN of the next, then synchronization is achieved automatically by updating the control register for all devices together. For MAX6952s, the devices can be synchronized by transmitting the serial data for the control register, and then toggling the CS pin for each device, either together or in quick succession. Figure 7 is the multiplex timing diagram. Blink Output The blink output indicates the blink phase, and is high during the P0 period and low during the P1 period. Blink phase status can also be read back as the P bit in the configuration register (Table 13). Typical uses for this output are: * To provide an interrupt to the processor so that segment data can be changed synchronous to the blinking. For example, a clock application may have colon segments blinking every second between hours and minute digits, and the minute display is best changed in step with the colon segments. Also, if the rising edge of blink is detected, there is half a blink period to change the P1 digit data. Similarly, if the falling edge of blink is detected, the user has half a blink period to change the P0 digit data.
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0010
RAM02
RAM18
0011
RAM03
RAM19
0100
RAM04
RAM20
0101
RAM05
RAM21
0110
RAM06
RAM22
0111
RAM07
RAM23
1000
RAM08
1001
RAM09
1010
RAM10
1011
RAM11
1100
RAM12
1101
RAM13
1110
RAM14
1111
RAM15
4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952
Table 15. Memory Mapping of User-Defined Font Register 0x05
ADDRESS CODE (HEX) 0x85 REGISTER DATA 0x00-0x7F SPI READ OR WRITE Read FUNCTION Read 7-bit user-definable font data entry from current font address. MSB of the register data is clear. Font address pointer is incremented after the read. Write 7-bit user-definable font data entry to current font address. Font address pointer is incremented after the write. Write font address pointer with the register data.
0x05 0x05
0x00-0x7F 0x80-0xFF
Write Write
Table 16. Font Pointer Address Behavior
FONT POINTER ADDRESS 0x80 to 0xF6 0xF7 0xF8 to 0xFF ACTION Valid range to set the font address pointer. Pointer autoincrements after a font data read or write, while pointer address remains in this range. Font address resets to 0x80 after a font data read or write to this pointer address. Invalid range to set the font address pointer. Pointer is set to 0x80 if address.
* If OSC is driven with an accurate frequency, blink can be used as a seconds counter or similar.
No-Op Register
A write to the no-op register is ignored.
Scan-Limit Register
The scan-limit register sets how many monocolor digits are displayed, either two or four. A bicolor digit is connected as two monocolor digits. The multiplexing scheme drives digits 0 and 1 at the same time, then digits 2 and 3 at the same time. To increase the effective brightness of the displays, drive only two digits instead of four. By doing this, the average segment current doubles, but also doubles the number of MAX6952s required to drive a given number of digits. Because digit 1 is driven at the same time as digit 0 (and digit 3 is driven at the same time as digit 2), only 1 bit is used to set the scan limit. The bit is clear if one or two digits are to be driven, and set if three or four digits are to be driven (Table 20). Change the scan-limit register only when the MAX6952 is in shutdown mode.
Selecting External Components RSET and CSET to Set Oscillator Frequency and Segment Current
The RC oscillator uses an external resistor RSET and an external capacitor CSET to set the oscillator frequency, fOSC. The allowed range of fOSC is 1MHz to 8MHz. RSET also sets the peak segment current. The recommended values of RSET and CSET set the oscillator to 4MHz, which makes the blink frequencies 0.5Hz and 1Hz. The recommended value of RSET also sets the peak current to 40mA, which makes the segment current adjustable from 2.5mA to 37.5mA in 2.5mA steps: ISEG = KI / RSET mA fOSC = KF / (RSET CSET + CSTRAY) MHz Where: KI = 2144 KF = 6000 RSET = external resistor in k CSET = external capacitor in pF CSTRAY = stray capacitance from OSC pin to GND in pF, typically 2pF The recommended value of RSET is 53.6k and the recommended value of CSET is 26pF.
Intensity Registers
Display brightness is controlled digitally by four pulsewidth modulators, one for each display digit. Each digit is controlled by a nibble of one of the two intensity registers, Intensity10 and Intensity32. The modulator scales the average segment current in 16 steps from a maximum of 15/16 down to 1/16 of the peak current. The minimum interdigit blanking time is, therefore, 1/16 of a cycle. The maximum duty cycle is 15/16. (Tables 21 and 22).
14
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952
Table 17. User-Definable Font Pointer Base Address Table
FONT CHARACTER RAM00 RAM01 RAM02 RAM03 RAM04 RAM05 RAM06 RAM07 RAM08 RAM09 RAM10 RAM11 RAM12 RAM13 RAM14 RAM15 RAM16 RAM17 RAM18 RAM19 RAM20 RAM21 RAM22 RAM23 ADDRESS CODE (HEX) 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 REGISTER DATA (HEX) D7 0x80 0x85 0x8A 0x8F 0x94 0x99 0x9E 0xA3 0xA8 0xAD 0xB2 0xB7 0xBC 0xC1 0xC6 0xCB 0xD0 0xD5 0xDA 0xDF 0xE4 0xE9 0xEE 0xF3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 D5 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 REGISTER DATA D4 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 1 D3 0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 D2 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
The recommended value of R SET is the minimum allowed value since it sets the display driver to the maximum allowed segment current. RSET can be set to a higher value to set the segment current to a lower peak value where desired. The user must also ensure that the peak current specifications of the LEDs connected to the driver are not exceeded. The effective value of CSET includes not only the actual external capacitor used, but also the stray capacitance from OSC to GND. This capacitance is usually in the 1pF to 5pF range, depending on the layout used.
register). In display-test mode, eight digits are scanned and the duty cycle is 7/16 (half power). Table 23 lists the display-test register format.
Applications Information
Choosing Supply Voltage to Minimize Power Dissipation
The MAX6952 drives a peak current of 40mA into LEDs with a 2.4V forward-voltage drop when operated from a supply voltage of at least 3.0V. The minimum voltage drop across the internal LED drivers is, therefore (3.0V 2.4V) = 0.6V. If a higher supply voltage is used, the driver absorbs a higher voltage, and the driver's power dissipation increases accordingly. However, if the LEDs used have a higher forward voltage drop than 2.4V, the supply voltage must be raised accordingly to ensure that the driver always has at least 0.6V headroom.
15
Display-Test Register
The display-test register switches the drivers between one of two modes: normal and display test. Display-test mode turns all LEDs on by overriding, but not altering, all control and digit registers (including the shutdown
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952
Table 18. User-Definable Character Storage Example
FONT CHARACTER RAM00 RAM00 RAM00 RAM00 RAM00 RAM01 RAM01 RAM01 RAM01 RAM01 RAM02 RAM02 RAM02 RAM02 RAM02 FONT ADDRESS POINTER 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E ADDRESS CODE (HEX) 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 FONT POINTER ADDRESS (HEX) 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E REGISTER DATA D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 D5 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 D4 1 1 0 0 1 0 0 1 0 0 0 0 1 0 0 D3 1 0 1 0 1 0 0 1 0 0 0 0 0 1 0 D2 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 D1 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 D0 0 1 1 1 0 0 0 1 0 0 0 1 1 1 0
Table 19. Setting a Font Character to RAM Example
ADDRESS CODE (HEX) 0x05 0x05 0x05 0x05 0x05 0x05 REGISTER DATA (HEX) 0x8A 0x42 0x61 0x51 0x49 0x46 ACTION BEING PERFORMED Set font address pointer to the base address of font character RAM02. 1st 7 bits of data: 1000010 goes to font address 0x8A; pointer then autoincrements to address 0x8B. 2nd 7 bits of data: 1100001 goes to font address 0x8B; pointer then autoincrements to address 0x8C. 3rd 7 bits of data: 1010001 goes to font address 0x8C; pointer then autoincrements to address 0x8D. 4th 7 bits of data: 1001001 goes to font address 0x8D; pointer then autoincrements to address 0x8E. 5th 7 bits of data: 1000110 goes to font address 0x8E; pointer then autoincrements to address 0x8F.
Table 20. Scan Limit Register Format
SCAN LIMIT Display digits 0 and 1 only Display digits 0, 1, 2, and 3 ADDRESS CODE (HEX) 0x03 0x03 D7 X X D6 X X D5 X X REGISTER DATA D4 X X D3 X X D2 X X D1 X X D0 0 1 HEX CODE 0xX0 0xX1
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952
Table 21. Intensity Register Format for Digit 0 (Address 0x01) and Digit 2 (Address 0x02)
DUTY CYCLE 1/16 (min on) 2/16 3/16 4/16 5/16 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16 15/16 (max on) TYPICAL SEGMENT CURRENT (mA) 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35 37.5 37.5 ADDRESS CODE (HEX) 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 See Table 22. D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX CODE 0xX0 0xX1 0xX2 0xX3 0xX4 0xX5 0xX6 0xX7 0xX8 0xX9 0xXA 0xXB 0xXC 0xXD 0xXE 0xXF
Table 22. Intensity Register Format for Digit 1 (Address 0x01) and Digit 3 (Address 0x02)
DUTY CYCLE 1/16 (min on) 2/16 3/16 4/16 5/16 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16 15/16 (max on) TYPICAL SEGMENT CURRENT (mA) 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35 37.5 37.5 ADDRESS CODE (HEX) 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 0x01, 0x02 D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 See Table 21. D3 D2 D1 D0 HEX CODE 0x0X 0x1X 0x2X 0x3X 0x4X 0x5X 0x6X 0x7X 0x8X 0x9X 0xAX 0xBX 0xCX 0xDX 0xEX 0xFX
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17
4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952
Table 23. Display-Test Register Format
REGISTER DATA MODE Normal operation Display test ADDRESS CODE (HEX) 0x07 0x07 D7 X X D6 X X D5 X X D4 X X D3 X X D2 X X D1 X X D0 0 1
The voltage drop across the drivers with a nominal 5V supply (5.0V - 2.4V) = 2.6V is nearly 3 times the drop across the drivers with a nominal 3.3V supply (3.3V 2.4V) = 0.9V. In most systems, consumption is an important design criterion, and the MAX6952 should be operated from the system's 3.3V nominal supply. In other designs, the lowest supply voltage may be 5V. The issue now is to ensure the dissipation limit for the MAX6952 is not exceeded. This can be achieved by inserting a series resistor in the supply to the MAX6952, ensuring that the supply decoupling capacitors are still on the MAX6952 side of the resistor. For example, consider the requirement that the minimum supply voltage to a MAX6952 must be 3.0V, and the input supply range is 5V 5%. Maximum supply current is: 12mA + (40mA x 10) = 412mA Minimum input supply voltage is 4.75V. Maximum series resistor value is: (4.75V - 3.0V) / 0.412A = 4.25 We choose 3.3 5%. Worst-case resistor dissipation is at maximum toleranced resistance, i.e., (0.412A) 2 x (3.3 1.05) = 0.577W. We choose a 1W resistor rating. The maximum MAX6952 supply voltage is at maximum input supply voltage and minimum toleranced resistance, i.e., 5.25V - (0.412A x 3.3 0.95) = 3.97V.
sity dims uniformly as supply voltage drops out of regulation and beyond. The MAX6952 operates down to 2.5V supply voltage (although most displays are very dim at this voltage), provided that the MAX6952 is powered up initially to at least 2.7V to trigger the device's internal reset.
Computing Power Dissipation
The upper limit for power dissipation (PD) for the MAX6952 is determined from the following equation: PD = (V+ 12mA) + (V+ - VLED) (DUTY x ISEG N) where: V+ = supply voltage Duty = duty cycle set by intensity register N = number of segments driven (worst case is 10) VLED = LED forward voltage ISEG = segment current set by RSET PD = power dissipation, in mW if currents are in mA Dissipation example: ISEG = 40mA, N = 10, Duty = 15 / 16, VLED = 2.4V at 40mA, V+ = 3.6V PD = 3.6V (12mA) + (3.6V - 2.4V)(15 / 16 40mA 10) = 0.493W Thus, for a 36-pin SSOP package (TJA = 1 / 0.0118 = +85C/W from operating ratings), the maximum allowed ambient temperature TA is given by: TJ(MAX) = TA + (PD TJA) = +150C = TA + (0.493 +85C/W) So, TA = +108C. Thus, the part can be operated safely at a maximum package temperature of +85C.
Low-Voltage Operation
The MAX6952 works over the 2.7V to 5.5V supply range. The minimum useful supply voltage is determined by the forward voltage drop of the LEDs at the peak current ISEG, plus the 0.6V headroom required by the driver output stages. The MAX6952 correctly regulates ISEG with a supply voltage above this minimum voltage. If the supply drops below this minimum voltage, the driver output stages may brown out, and be unable to regulate the current correctly. As the supply voltage drops further, the LED segment drive current becomes effectively limited by the output driver's onresistance, and the LED drive current drops. The characteristics of each individual LED in a 5 7 matrix digit are well matched, so the result is that the display inten18
Power Supplies
The MAX6952 operates from a single 2.7V to 5.5V power supply. Bypass the power supply to GND with a 0.1F capacitor as close to the device as possible. Add a 47F capacitor if the MAX6952 is not close to the board's input bulk decoupling capacitor.
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952
ONE COMPLETE 1.4ms MULTIPLEX CYCLE AROUND 14 ROWS 100s COLUMN DRIVER PINS O14-O18 DIGIT 0 ROW 1 DIGIT 0 ROW 2 DIGIT 0 ROW 3 DIGIT 0 ROW 4 DIGIT 0 ROW 5 DIGIT 0 ROW 6 DIGIT 0 ROW 7 DIGIT 2 ROW 1 DIGIT 2 ROW 2 DIGIT 2 ROW 3 DIGIT 2 ROW 4 DIGIT 2 ROW 5 DIGIT 2 ROW 6 DIGIT 2 ROW 7 DIGIT 0 ROW 1 START OF NEXT CYCLE
COLUMN DRIVER PINS O19-O23
DIGIT 1 ROW 1
DIGIT 1 ROW 2
DIGIT 1 ROW 3
DIGIT 1 ROW 4
DIGIT 1 ROW 5
DIGIT 1 ROW 6
DIGIT 1 ROW 7
DIGIT 3 ROW 1
DIGIT 3 ROW 2
DIGIT 3 ROW 3
DIGIT 3 ROW 4
DIGIT 3 ROW 5
DIGIT 3 ROW 6
DIGIT 3 ROW 7
DIGIT 1 ROW 1
DIGIT 1 COLUMN DRIVER OUTPUTS PINS O19-O23 1/16TH (MIN ON) 2/16TH
DIGIT 1 ROW 1's 100s MULTIPLEX TIMESLOT CURRENT SOURCE HIGH-Z CURRENT SOURCE HIGH-Z CURRENT SOURCE
3/16TH CURRENT SOURCE 4/16TH CURRENT SOURCE 5/16TH CURRENT SOURCE 6/16TH CURRENT SOURCE 7/16TH CURRENT SOURCE 8/16TH CURRENT SOURCE 9/16TH CURRENT SOURCE 10/16TH CURRENT SOURCE 11/16TH CURRENT SOURCE 12/16TH CURRENT SOURCE 13/16TH CURRENT SOURCE 14/16TH CURRENT SOURCE 15/16TH CURRENT SOURCE 16/16TH (MAX ON) DIGITS 0 & 1 ROW OUTPUTS PINS O0-O6 DIGITS 2 & 3 ROW OUTPUTS PINS O7-O13 HIGH-Z LOW HIGH-Z
HIGH-Z HIGH-Z HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z HIGH-Z HIGH-Z MINIMUM 6.25s INTERDIGIT BLANKING INTERVAL HIGH-Z
HIGH-Z
Figure 7. Multiplex Timing Diagram (OSC = 4MHz) ______________________________________________________________________________________ 19
4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver MAX6952
Board Layout
When designing a board, use the following guidelines: 1) The RSET connection to the ISET pin is a high-impedance node, and sensitive to layout. Place RSET right next to the ISET pin and route RSET directly to these pins with very short tracks. 2) Ensure that the track from the ground end of RSET routes directly to GND pin 18 (PDIP package) or GND pin 16 (SSOP package), and that this track is not used as part of any other ground connection.
Chip Information
TRANSISTOR COUNT: 43,086 PROCESS: CMOS
Pin Configurations
TOP VIEW
O0 O1 O2 GND GND GND O3 O4 O5 O6 O7 O8 O9 O10 O11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 40 39 38 37 36 35 34 33 32 O23 O22 O21 V+ V+ V+ O20 O19 O18 O17 O16 O15 O14 O13 O12 N.C. OSC CS DOUT CLK O0 O1 O2 GND GND O3 O4 O5 O6 1 2 3 4 5 6 7 8 9 36 O23 35 O22 34 O21 33 V+ 32 V+ 31 O20 30 O19 29 O18
MAX6952
28 O17 27 O16 26 O15 25 O14 24 O13 23 O12 22 OSC 21 CS 20 DOUT 19 CLK
MAX6952
31 30 29 28 27 26 25 24 23 22 21
O7 10 O8 11 O9 12 O10 13 O11 14 ISET 15 GND 16 BLINK 17 DIN 18
N.C. 16 ISET GND BLINK DIN 17 18 19 20
SSOP
PDIP
20
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4-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7 Matrix LED Display Driver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SSOP.EPS
MAX6952
36
INCHES DIM A A1 B C e E H L D MAX MIN 0.096 0.104 0.004 0.011 0.012 0.017 0.009 0.013 0.0315 BSC 0.291 0.299 0.398 0.414 0.040 0.020 0.598 0.612
MILLIMETERS MAX MIN 2.65 2.44 0.29 0.10 0.44 0.30 0.23 0.32 0.80 BSC 7.40 7.60 10.11 10.51 0.51 15.20 1.02 15.55
E
H
1
TOP VIEW
D A1 e A
C 0 -8
B
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 36L SSOP, 0.80 MM PITCH
APPROVAL DOCUMENT CONTROL NO. REV.
21-0040
E
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
21 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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